1. Field of the Invention
The present invention relates to a semiconductor ROM memory device and corresponding fabrication method and, more particularly, to a two layer metal CMOS ROM in which programming is accomplished upon deposition of the second metal layer.
2. Description of the Related Art
Semiconductor memory devices are widely used in digital systems including minicomputers, microprocessors, microcontrollers and computing systems. Storage of fixed programs is often furnished in these systems using MOS read only memory devices, called ROMs. ROMs are fabricated by semiconductor manufacturers by special order, in which the program code fixed into the ROM is specified by the customer. The manufacturing process is lengthy, requiring many steps, with the steps extracting a cost in time, handling of materials and inventory storage and handling of finished circuits. It is beneficial to a customer, and therefore to a manufacturer, that turn-around time, the cycle time between receipt of the custom-order ROM code and delivery of finished ROMs, be as short as possible. It is thus advantageous that ROM code programming be accomplished as late as possible in the manufacturing process. However in conventional fabrication of ROM cells, ROM programming occurs very early in the manufacturing process. For example, ROMs have been programmed by implanting ions prior to forming the polysilicon gate, an early step of the fabrication process.
Furthermore, in microcontrollers and microprocessors, advantageous operating capabilities result when on-chip ROM is used for program memory storage. On-chip ROM is a ROM memory array which is combined with other, non-memory types of circuits on a single integrated circuit chip. For example, a single-chip microcontroller may include an on-chip ROM which stores operating system program code. The usage of an on-chip ROM advantageously increases the operating speed of a computer system and reduces manufacturing and product costs. Economics of the manufacture of ROMs, particularly the economics of fabricating microprocessors and microcontrollers with on-chip ROMs, dictate that manufacturing costs be kept to a minimum. The complexity and cost of the fabrication process have a major impact on the overall manufacturing cost. Thus, it is greatly advantageous for on-chip ROMs to be fabricated in the same manufacturing process as the rest of the chip.
One method of fabricating a programmable MOS ROM is taught in U.S. Pat. No. 4,384,399 ('399), entitled "Method of Making a Metal Programmable Read Only Memory Device" to C. K. Kuo, which issued May 24, 1983. This patent describes a method of fabricating a metal programmable ROM using a single-metal layer, metal-gate MOS process. The ROM is programmed at the time the metal level of contacts and interconnections is patterned. Each potential MOS transistor in the array is programmed by patterning the metal using a photoresist mask and etch sequence in which an aperture open area, leaving exposed a gate oxide layer, is defined over each cell to be programmed as a logic "0" and each cell to be programmed as a logic "1" is left covered by metal to furnish a gate for the transistor. The logic "1" cells are not actual transistors but are instead stateless "non-transistors". After the metal layer is formed, the array is subjected to a boron ion implant which penetrates the gate oxide in exposed areas (logic "0" areas) to create an implanted region in the channel area which raises the threshold high enough so that charge spread in the channel region does not turn on the stateless non-transistor.
The U.S. Pat. No. '399 method disadvantageously requires an irregular manufacturing process having an ion implant following metal masking. The additional ion implant step increases the complexity, handling and processing time of the fabrication process. The requirement of a nonstandard manufacturing process greatly increases manufacturing and product costs.
An additional method of fabricating a programmable MOS ROM is taught in U.S. Pat. No. 4,390,971 ('971), entitled "Post-Metal Programmable MOS Read Only Memory", to C. K. Kuo and issued on Jun. 28, 1983. In a silicon-gate MOS process, the ROM is programmed following the deposition and patterning of a metal level of contacts and interconnections. An array of MOS transistors are formed prior to the deposition of the metal layer, setting all of the cells to a logic "1" value. Each cell in the array is selected to be programmed a logic "1" or a logic "0" by implanting ions through the polysilicon gates and thin gate oxide layer, using a patterned protective oxide as a mask or using photoresist as a mask prior to application of the protective oxide layer. The programming of the ROM bit-cells is done by controlling the transistor threshold voltage. In logic "1" memory cells, an implant is performed through the polysilicon gates and thin gate oxide, resulting in a higher transistor threshold voltage that consequently does not allow turn-on of the transistor. The logic "0" memory cells are regular N-channel transistors.
The U.S. Pat. No. '971 method, like the U.S. Pat. No. '399 method, disadvantageously requires a manufacturing process which is non-standard and highly irregular. The requirement of a nonstandard manufacturing process greatly increases manufacturing and product costs.
A further method of fabricating a programmable MOS ROM is taught in U.S. Pat. No. 4,326,329 ('329), entitled "Method of Making a Contact Programmable Double Level Polysilicon MOS Read Only Memory", to D. J. McElroy and issued on Apr. 27, 1982. In the MOS process of the U.S. Pat. No. '329 patent, address lines are formed in a metal layer, gates are formed in a second level of polysilicon beneath the metal strip, and output and ground lines are defined by elongated N.sup.+ regions in the silicon wafer. Each potential MOS transistor in the array is programmed to be a logic "1" or a logic "0" by presence or absence of a contact which engages the polysilicon gate to the metal strip.
While the U.S. Pat. No. '329 patent method of programming of the ROM cells in the contact layer advantageously delays the programming step in comparison to conventional ROM programming techniques, several process steps remain following the programming step. The programming step of patterning a multilevel oxide layer, exposing selected gates in a ROM array area, is performed at least one mask step from the completion of the silicon processing. For example, a metal layer must be formed before processing is complete. It is desirable to delay the programming step further in the ROM fabrication process.
Furthermore, the U.S. Pat. No. '329 patent method of programming the ROM bit-cells by connecting or not connecting the ROM cell transistor gate to a metal address line results in many transistors with unconnected, floating gates. The presence of floating gates violates typical circuit design rules and elevates the risk of reliability problems.
The manufacturing processes which incorporate the U.S. Pat. No. '329, '971 and '399 patent methods are special processes which are different from a conventional CMOS polysilicon gate manufacturing process which is commonly used to fabricate microcomputers, microprocessors and microcontrollers and requires additional fabrication steps. Unfortunately each nonstandard step of a fabrication process raises the complexity and the cost of producing an integrated circuit chip.